1. Field of the Invention
This invention relates generally to computers, and in particular, to systems utilized in computers to access dynamic random access memory (DRAM).
2. Description of the Related Technology
Personal computers are becoming more prevalent in the work place with more and more people depending on their livelihoods from the use thereof. Advances in computer technology have created the ability and thus the demand for increased memory capacity, faster program computation, higher display resolution and faster presentation of information to the computer user. This demand for computers may be directly attributable to the high speed operation of present microprocessors and the availability of megabytes of system memory.
Low cost system memory is made possible by the use of high density transistor memory consisting of dynamic random access memory ("DRAM") integrated circuits having millions of transistors and capable of storing megabytes of information. Fast and high capacity DRAM has substantially improved the speed of operation, ease of use, and data storage capacity of a personal computer.
Each personal computer system typically uses at least one megabyte of system memory and typically, four or more megabytes. Presently, DRAMs are manufactured in one, four and sixteen megabit capacities, while the future promises capacities of 64 megabits for integrated circuit DRAMs. There is a unique address for each individual piece of information stored in the DRAM. Address selection is accomplished by using binary numbers which are represented by either a "0" or a "1" and have values of ##EQU1## where n is the number of binary digits and n=20 for a one megabit binary number. Thus, a 20 digit binary number is required to represent a unique address for a one bit wide memory cell in a one megabit storage capacity DRAM. One megabit DRAMs may also be configured as 4 bits by 256K (where K=1024), which requires an 18 digit binary number for address selection.
A DRAM integrated circuit, therefore, must have a sufficient number of connections ("pins") to accept the address for one of its memory cell locations. As mentioned previously, one megabit in the binary number system requires 20 binary digits or, in terms of electrical connections, requires 20 pins on a one megabit DRAM integrated circuit. In addition, the DRAM requires other control signals and, of course, the data input and output connections; thus, in large capacity DRAMs a problem exists in the number of connections that must be placed physically on the DRAM integrated circuit.
The greater the number of pins that are required on an integrated circuit, the larger the physical package must be. Size is a major factor in cost and utilization in high density printed circuit boards. The semiconductor and computer industries have compromised in the manufacture and use of DRAM integrated circuits by optimizing size and price with data access speed. Multiplexing the address pins greatly reduces the size and cost of DRAM integrated circuits.
To multiplex DRAM address pins, the DRAM integrated circuit is designed with its addressing configured into a two dimensional X-Y matrix with the X axis called "rows" and the Y axis called "columns". Normally, the lower order binary address digits or "address bits" are represented by the columns and the higher order binary address digits by the rows. Therefore, when addressing a DRAM address, the row address bits may first be presented on the DRAM address pins, stored into the internal DRAM logic by a row address control signal, and then the remaining column address bits may next be presented on the same DRAM address pins to complete the entire binary memory address.
DRAM integrated circuits are slower in operation, however, than the microprocessor, therefore the computer system typically must wait a certain amount of time for each DRAM access operation. A typical DRAM memory controller introduces "wait states" into a DRAM memory access request from the microprocessor or other bus master of the computer system. The memory access cycle is delayed by these wait states for both row and column address selection of the DRAM and comprise the majority of the time required for the access cycle.
In a computer system, a plurality of DRAM integrated circuits may be arranged into common row and column addresses to provide the required data word width, for example, in eight bit bytes and 16 or 32 bit words. As those of ordinary skill in the art will readily appreciate, in order to provide the data word size required, DRAMs must be arranged with the same, or common, row and column address such that for each address generated, each DRAM will deliver its portion of the data word associated with that address. A plurality of contiguously addressed bytes may be further grouped together as, for example, 64 kilobytes and will be referred to hereinafter as "pages" of memory. There is a unique row address for each of these pages of memory. Each page of memory utilizes the column address lines to select the unique binary address of an individual byte within the page. Within a page of memory, the least significant bits of the column address are utilized for rapid multiple data transfers between the memory and the computer system central processing unit ("CPU"). Rapid transfer of data located in multiple memory locations may be called "page mode" or "burst transfer" of the data.
Normally, within a page of memory, the row address is selected once and not changed by the memory controller logic while the column addresses select the desired memory locations within the selected memory page. A problem exists, however, when a new page of memory must be addressed. A new page of memory requires a new row address which requires that the new row address be placed on the DRAM integrated circuit address pins and asserted into the DRAM internal address multiplexing storage register by a row address strobe ("RAS") signal. The column address must then be placed on the DRAM integrated circuit address pins and asserted into the DRAM by a column address strobe ("CAS") signal for selection of the desired memory location.
Having to select the row address before selecting the column address, because of the multiplexing requirements of the DRAM, creates the need to generate a number of wait states by the DRAM controller logic. What is needed is a way to reduce the number of wait states required during DRAM access operations by the computer system.